CMPE 424: Digital System Design

Category: Junior
Quarter: Winter 2002-2003
Units: 4
Course Status: Core Course for Computer Engineering majors 
Pre-requisite: Computer Organization and Assembly Language
Instructor: Dr. Shahid Masud
Office & E-mail: Room 2xx
Office Hours: Tue & Thu 1100-1300h

Teaching Assistant: Muhammad Usman Ilyas
Office & E-mail: Room 210
Office Hours: Mon & Wed 1130-1230h in DR-16
Grading Scheme:
  • Quizzes(3): 15%
  • Labs(8): 15%
  • Design Exercise: 20%
  • Midterm: 20%
  • Final: 30%
  • Lectures and Examinations:
  • Two weekly lectures of 100 minutes each.
  • One lecture session will be in the computer lab.
  • Attendance is not compulsory, punctuality is desired.
  • One in-class midterm.
  • Comprehensive final examination.
  • Course Description:
        This course explains how to go about designing complex, high-speed digital systems. The use of modern EDA tolls in the design, simulation and implentation is explored. A hardware description language such as Verilog or VHDL will be taught to model digital systems at Behaviour and RTL level. The field programmable gate arrays (FPGA) are used in the laboratory exercises as a vehicle to understand complete design-flow. Advanced methods of logic minimisation and state-machine design are explained. The working of complex logic and memory building blocks such as memory chips, arithmetic circuits, digital processors, UARTs etc. is discussed. The BIST and scan techniques for testing of digital systems are also covered.

        Required:  Advanced Digital Design with Verilog HDL by Michael D. Ciletti
                           Latest Edition, Prentice Hall
        Supplementary Reading:  Digital Design Principles and Practices by Jon F. Wakerly
                           2002 Edition, Pearson Education

       Xilinx Synthesis Book is here


    Introduction to Digital System Design
    Chap 1
    Review of Combinational Logic Design
    Chap 2
    Logic Minimisation techniques - McCluskey method
    Chap 2
    Sequential Logic Design
    Chap 3
    State Machine Minimisation - ASM techniques
    Chap 3
    6 (1/2)
    6 (2/2)
    Programmable Logic Devices - FPGA, CPLD
    Chap 8
    Architecture for Arithmetic Processors
    Chap 10
    Architecture for Arithmetic Processors
    Chap 10
    Architecture for Digital Signal Processors
    Chap 9
    Design for test
    Chap 11